Integrated circuits (“ICs”) vary in complexity from, for example, an analog circuit comprising only a few basic electronic components, such as transistors and diodes, to a complex digital system including hundreds of millions of transistors. Although different design methods and Electronic Design Automation (“EDA”) tools are arranged to design ICs of various levels of complexity, the fundamental process of IC design remains unchanged. That is, IC design engineers design an integrated circuit by transforming a circuit specification into geometric descriptions of physical components that creates the basic electronic components. In general, the geometric descriptions are polygons of various dimensions, representing conductive features located in different processing layers. The detailed geometric descriptions of physical components are generally referred to as integrated circuit layouts. After the creation of an initial integrated circuit layout, the integrated circuit layout is usually tested and optimized through a set of steps in order to verify that the integrated circuit meets the design specification and will perform as desired.
Shown in FIG. 1 is a flowchart that illustrates the common post-design testing and optimization steps. After an integrated circuit design process is completed (shown at 2), an initial integrated circuit layout is created (shown at 4). The layout is first design-rule checked and then verified to be equivalent with the desired design schematic. This step (shown at 6) is generally referred to as design-rule check (DRC) and layout versus schematic (LVS).
The step of RC extraction (shown at 8) is subsequently performed in order to “extract” electrical characteristics of the layout. The common electrical characteristics that are extracted from an integrated circuit layout include capacitance and resistance in the electronic devices and on the various interconnects (also generally referred to as “nets”) that electrically connect the aforementioned devices. The current step is also referred to as “parasitic extraction” because these capacitance and resistance values are not intended by the designer but rather result from the underlying device physics of the device configurations and materials used to fabricate the IC.
The designed IC is then simulated (shown at 10) to insure the design meets the specification with the parasitic capacitance and resistance in the IC. If the parasitic capacitance and resistance causes undesirable performance, the integrated circuit layout is typically changed through one or more design optimization cycles. If the simulation results satisfy the design specification, the design process is completed (shown at 12).
It is known that the parasitic capacitance and resistance can cause various detrimental effects in a designed IC, such as undesired long signal delays on the nets. Thus, the impact of the parasitic capacitance and resistance on the performance of the designed IC must be accurately predicted so that design engineers can compensate for these detrimental effects through proper design optimization steps.
It is also recognized that, when device feature sizes shrink down to the ultra-deep submicron range (less than 0.25 micron), interconnect delays begin to dominate the total delay in an IC. Moreover, because of the reduced contact-to-gate electrode distance and increased device density in ICs made with advanced technology, contact/via capacitance accounts for an increasing proportion of the total interconnect delay, when compared with coupling capacitance between adjacent nets.
The existing extraction methodology is problematic in contact/via parasitic capacitance extraction. Currently, extraction efforts are mainly focused on the coupling capacitance between adjacent nets. The parasitic effects on the contacts and vias are addressed with much less accuracy. The lack of extraction accuracy on contact and via capacitance may cause large discrepancies between simulated results and actual circuit performance.
As an example, an existing full-chip extracting system is typically “polygon-based.” In extracting a design layout, a circuit layout is first divided into small pieces wherein each small piece contains a recognized primitive polygon pattern (also generally referred to as primitive). The extraction system, then, extracts parasitic values (e.g., resistance, capacitance) by reading a pre-made, parasitic capacitance/resistance look-up table typically stored in a technology file (shown at 9) for the per-unit parasitic value of such a primitive polygon pattern. The full-chip parasitic value is usually obtained by arithmetic operations on the primitive geometric patterns. The actual contact/via shapes and size variations are generally ignored by the extracting system.
FIG. 2A shows a perspective view of a MOSFET transistor occurring in an IC, where contacts “C” having a cylindrical shape and variation in size are made from the first interconnect layer “M1” to the source/drain regions “S” and “D.” In an existing parasitic extracting system as described above, the actual contact shape and variation in size are not taken into account. Instead, a per-unit capacitance value, usually derived from an ideal, square-shaped contact primitive, is usually used to calculate the contact-to-gate-electrode parasitic capacitance in the transistor. As a result, the simulated results can be overly pessimistic with a margin of over 10%.
FIG. 2B shows a perspective view of a portion in an IC, where vias having a cylindrical shape and variation in size are formed between the first interconnect layer “M1” and the second interconnect layer “M2.” Similarly, during RC extraction step 8 in an existing full-chip extracting system, parasitic capacitance between vias and via-to-metal-layer is roughly estimated without taking account of the actual via shape, via density and variation in size.